A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Field effect transistors, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), are now widely used within integrated circuits. As the dimensions of a MOSFET are further scaled down to submicron and nanometer dimensions, the short channel length of the MOSFET results in undesired short channel effects, as known to one of ordinary skill in the art. For example, the technical journal articles, Split-gate Field-effect Transistor by Michael Shur, Appl. Phys. Lett., 54 (2), pps. 162-164, Jan. 9, 1989, A Novel Hetero-Material Gate (HMG) MOSFET for Deep-Submicron ULSI Technology by Xing Zhou and Wei Long, IEEE Transactions on Electron Devices, Vol. 45, No. 12, December 1998, and Dual Material Gate Field Effect Transistor (DMGFET) by Wei Long and Ken K. Chin, IEDM, 1997, pps. 549-52, describe the disadvantageous short channel effects, that result for MOSFETs with short channel lengths of submicron and nanometer dimensions, such as threshold voltage roll-off and DIBL (Drain Induced Barrier Lowering).
Threshold voltage roll-off refers to a decrease in the threshold voltage of a MOSFET as the channel length of the MOSFET decreases at short channel lengths of submicron and nanometer dimensions. DIBL (Drain Induced Barrier Lowering) refers to a lowering of the potential barrier at the source of a MOSFET as the channel length of the MOSFET decreases at short channel lengths of submicron and nanometer dimensions. Threshold voltage roll-off and DIBL (Drain Induced Barrier Lowering) disadvantageously result in higher leakage current for a MOSFET having a short channel length of submicron and nanometer dimensions.
Despite such disadvantageous short channel effects, further reduction of the dimensions of the MOSFET is desired. Thus, the above mentioned technical journal articles describe a dual material gate MOSFET for minimizing such disadvantageous short channels effects for a MOSFET having short channel lengths of submicron and nanometer dimensions.
Referring to FIG. 1, such a dual material gate MOSFET 102 has a source 104 and a drain 106 within a semiconductor substrate 108 similar to a typical MOSFET. In addition, the dual material gate MOSFET 102 has a gate dielectric 110 disposed on a channel region of the MOSFET 102 similar to a typical MOSFET. Unlike a typical MOSFET however, the dual material gate MOSFET 102 has a conductive gate comprised of portions of two separate materials. The dual material gate MOSFET 102 is comprised of a first material gate portion 112 and a second material gate portion 114. The first material gate portion 112 is disposed toward the drain 106 of the dual material gate MOSFET 102, and the second material gate portion 114 is disposed toward the source 104 of the dual material gate MOSFET 102.
As described in the above mentioned technical journal articles, when the dual material gate MOSFET 102 is an N-channel MOSFET, the second material gate portion 114 that is disposed toward the source 104 has a higher work function than that of the first material gate portion 112 that is disposed toward the drain 106 in order to minimize the disadvantageous short channel effects within the MOSFET 102. Conversely, when the dual material gate MOSFET 102 is a P-channel MOSFET, the second material gate portion 114 that is disposed toward the source 104 has a lower work f unction than that of the first material gate portion 112 that is disposed toward the drain 106 in order to minimize the disadvantageous short channel effects within the MOSFET 102.
Given that a dual material gate may minimize the disadvantageous short channel effects within a field effect transistor, an effective process for fabricating a dual material gate within a field effect transistor is desired.